The present invention concerns hardware for reducing the amount of power consumed by the high speed random access memory (RAM) used in a computer system. Many computers are designed so that it is relatively easy to increase the amount of RAM which is installed in the computer. Typically, at least in "workstation" computers, it is common to provide a set of memory slots, into each of which can be inserted an additional memory module. As additional memory modules are added to the computer, however, the amount of power consumed by these memory modules can be quite significant. The result is an increase in the power, heat and cooling fan noise of the system. For an office environment, this increased heat and noise is very undesirable.
More generally, for high performance workstations, a high capacity memory system is desirable. Powerful computer systems tend to have multiple banks of memory to provide a large total capacity of memory to execute large programs, or multi-task between several smaller programs. However, the computer's central processor can only access one of the banks of memory at a given instant in time.
In prior art multiple bank memory systems, it is quite typical to only activate the memory chips for the active bank. However, the idle memory banks still receive address, data and clock signals, which are used only by the active memory bank. In a large memory system, the energy associated with switching these signals to the idle banks of memory chips consumes a significant amount of power.
The present invention implements a clocking scheme on the memory modules such that only the active memory module is clocked. In other words, only the active memory module receives data, address and clock signals. This eliminates all of the electrical switching on the idle memory modules, except for dynamic refresh cycles. As a result there is a dramatic decrease in system power and cooling requirements.